Use the following settings as simulation input

Specification	Value
Replacement Policy	LRU
Scheduling Mechanism	Priority Based
CPU Time slice	1
Use Random Access Sequence	NO
Number of Tasks	5
Number of memory references for Task A,B,C,D,E	5 each
Priority A,B,C,D,E	3, 1, 0, 2, 4

Memory references of each task

# 5	52	93	113	28	9
# 4	29	93	113	28	9
# 3	19	93	104	125	9

# 2	93	19	104	89	31
# 1	19	76	113	125	9
Task	A	B	C	D	E

(i) Compile the hit rate in each of the following caches after 12 simulation cycles.

(6 marks)

Cache Hit Rate % Cache Size, # Sets	FIFO	Round Robin		Priority Based 3-1-0-2-4 priority
		CPU Time Slice = 1	CPU Time Slice = 14
16, 4
16,8
32,2

(ii) When does the round robin technique behave like the FIFO technique?

(Hint: try various Time Slice values to see their effect)

(2 marks)

(iii) When can the priority-based technique behave like the round robin technique?

(Hint: try various Priority configurations to see their effect)

(2 marks)