Use VHDL to design a Bubble Sort Digital System , create two models, one for the Data Path section, and the other for the Controller FSM section, then integrate these two models into the final BubbleSortDigitalSystem model .Then create a test bench model that instantiates the model, and uses some processes to apply a clock to the system, and to load initial data into the system before asserting the input signal. Then wait for the Sort to be completed. Then proceed to read all ten value and verifying that they are output in order at the OutData_H(7:0) output bus.

Use the diagrams below to create the VHDL code models.

VI EN-u VI EN-u