Use Vivado to create a project. Write your own VHDL code which uses a case statement

and one or more if$-$else$-$endif statements within the case statement, all within a process block

describing combinational logic, to implement a function $($your choice$),$ where the entity outputs

are a function of the entity inputs $($remember$,$ if you do NOT connect your VHDL statement

inputs and outputs to the entity inputs and outputs, Vivado will simply delete the statements you

write$).$ You are allowed to change the entity inputs and outputs names, size and directions to anything you like, i$.$e$.,$ they do NOT need to use those given in the VHDL of part A above. But you

are not permitted to copy VHDL from any other assignments or from other publicly available

sources. Open $$elaborated design$$ and identify components of the schematic that correspond to

elements of the VHDL code. Please title $$Lab #$3$: Behavioral$-$to$-$Schematic Translation, Case and

If$-$Else$-$Endif Statements$$