Question: Using DC simulations, plot the Gate characteristics (Drain Current on Y-axis Vs Gate Voltage on X-axis) on a linear and log scale (Y-axis) of the

Using DC simulations, plot the Gate characteristics (Drain Current on Y-axis Vs Gate Voltage on X-axis) on a linear and log scale (Y-axis) of the following Transistors whose models are available in the ASAP 7nm PDK provided. Assume a Supply Voltage, VDD = 0.7V and a width of '3 fins' for each of the transistors (i) - (iii) and a width of 1 fin for SRAM NFET and a width of 1 fin for the SRAM PFET

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