Using full VHDL descriptions, design and implement a finite state machine described by the

following state transition diagram.

$($ULO $3,4,5)[10$ Marks$]$

A$.$ Design the module entity including library state declaration. $($ULO $4,5)[1+1\mathrm{.}5$ Marks$]$

B$.$ Design the module architecture

$($ULO $3,5)[5+2\mathrm{.}5$ Marks$]$