Using Verilog, design a linear interpolator that would double the sampling frequency. The code should be parametrizable with a flexible word size, but you can assume that it will always double the sampling frequency by inserting one sample between adjacent samples received. The inserted interpolated word should represent the average of the two received samples. The output should be operating at the faster clock, and the input should update at the slower clock frequency. This should be clear in the test bench. The module should have a reset. Show and explain your verilog code for the interpolator, the test bench, and simulation results.