Question: Using Verilog language design and verify a FP adder using single precision IEEE 754 format. The inputs are assumed to be normalized and your design

Using Verilog language design and verify a FP adder using single precision IEEE 754 format. The inputs are assumed to be normalized and your design should generate a normalized output. The adder can be of any type however to get higher grade, design a faster adder. draw the ASMD chart and write the code

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