Using VHDL, design a package sorter to classify packages based on their weights and to keep track of packages of different categories. The sorter has a Reset and will keep track of packages since the last Reset. Packages should be classified into 5 groups: 1. between 1 and 200 grams 2. between 200 and 500 grams 3. between 500 and 800 grams 4. between 800 and 1000 grams 5. greater than 1000 grams Design a Digital System to sort packets based on the weights. You need to decode weight measurements and classify them into various groups. The input to the Digital System will be a 10 bit unsigned binary number (indicating the weight of the package), a clock signal, and a reset. One of the outputs will be a 3 bit unsigned number representing the current package group number. There will also be five 8 bit unsigned outputs representing the number of items weighed in each category since the last reset. The reset line is provided as input to allow these counts to be cleared. The output lines have the following functionality: currentGrp(2:0): Outputs the group number for the weight currently being applied to the sorter. When a weight of zero is applied, it should output a zero. Grp1-Grp5: Outputs the number of pacakges that have been weighed as belonging to each group since the last reset. These outputs should be zero when reset=0. All state changes to the outputs should occur on the rising edge of the clock. Notice that the clk signal will be significantly faster than the duration of the weight signal. As such, you must ensure that the count is only updated once for a given object. Secondly, new packages can only be detected and sorted if the weight is allowed to go to zero between one package and the next. This is to ensure that any fluctuations in the weight after it has been sampled are not considered new items. Example input sequence: Reset sorter Put 250grams on Take off Put on 300 grams Take off Put on 501grams Add 512 grams to original weight At the end of this sequence, the grp1=grp4=grp5=0x00, grp2=0x02, grp3=0x01, currentGrp=0x5 Test your design by using a VHDL testbench that instantiates and provides different unsigned integer values to the Weight input. The testbench should use 2 arrays (one to set the input weights, one to store the expected group counts and currentGrp values after each package is taken-off ). Finally, synthesize your design using the Xilinx tools as before, but you do not need to program the board for this question. Simply report the results of the synthesis (total slices, total delay) for the circuit. Submission Instructions: Submit your VHDL code, your test bench code, your simulations results (Waveform only), and the synthesis reports (circle the #of slices, critical delay)