Verilog Code for the following Schematic, the previous two assignments can be called or implemented. I will rate answer ASAP

Using Verilog behavioral specification and codes from previous two assignments, design and simulate the following datapath, whose schematic is shown below. Numbers A, B and C are 12-bit integers. Define all modules so that you have to describe redundant sub-circuits only once. Include a top-level stimulus module (test bench) that will exercise your design. Apply a variety (couple dozen) combinations of the test vectors for X and Y inputs 1. RA Output Rc