VERILOG HELP Tasks for second week: 2. Design and functionally verify the control unit (CU). You should use the systematic design methodology taught in class to design the CU (FSM), i.e., starting with constructing an ASM chart that describes the cycle-by-cycle operation of the system (the calculator in this case), then extract the state transition diagram and output table for describing (in HDL) the FSMs next-state logic and output logic respectively. The FSM must be tested thoroughly via functional verification, i.e., all designed state transitions as well as the corresponding outputs must be checked.

Integrate and functionally verify the entire system. You should write a top-level Verilog design code for the calculator by connecting the FSM with the DP, and write a Verilog testbench to verify the overall systems functional correctness. Hint: Remember to check the DONE flag to know when the state machine has finished running. Use a self-checking testbench for functional verification of the integrated system