Verilog: How do I use an input in an if statement? Please explain to me how to fix this particular problem, and what the fix is. The problem is in the only if statement, thanks!

Here is my code:

`default_nettype none

//Note - direction 0 is right shift, direction 1 is left shift.

module ShiftReg(input data, input clk, input direction, output [3:0] out); //input dir = direction; reg [3:0] reg_out;

always @ (posedge clk) begin if(direction == 1) { reg_out[1] <= reg_out[0]; reg_out[2] <= reg_out[1]; reg_out[3] <= reg_out[2]; reg_out[0] <= data; } else{ reg_out[0] <= reg_out[1]; reg_out[1] <= reg_out[2]; reg_out[2] <= reg_out[3]; reg_out[3] <= data; }

end

assign out = reg_out; endmodule

Here is the error I receive from testing:

design.sv:12: syntax error design.sv:12: error: malformed statement design.sv:16: syntax error design.sv:18: Syntax in assignment statement l-value. design.sv:22: syntax error design.sv:26: Syntax in assignment statement l-value. design.sv:28: syntax error testbench.sv:1: error: `default_nettype directives must appear testbench.sv:1: : outside module definitions. The containing testbench.sv:1: : module ShiftReg starts on line design.sv:5. testbench.sv:3: error: malformed statement testbench.sv:5: syntax error testbench.sv:5: Syntax in assignment statement l-value. testbench.sv:7: syntax error testbench.sv:7: error: malformed statement testbench.sv:8: syntax error testbench.sv:8: error: malformed statement testbench.sv:10: syntax error testbench.sv:10: error: malformed statement testbench.sv:12: syntax error testbench.sv:13: error: malformed statement Exit code expected: 0, received: 1