Verilog practice problems

1.how would you change the code to make the reset signal synchronous?

2.How would you write a case statement for this?

Architecture behavior of specific_counter_case Is Signal count_int: STD LOGIC VECTOR (2 downto 0) begin count countint countint countint countint count int"01O"; when "010" > count int"000" when others => - - - - count int countint countint countint countint count int"01O"; when "010" > count int"000" when others => - - - - count int