Question: VHDL code in equations form Arithmetic Comparison Design A comparator compares the relative sizes of two numbers. Consider a comparator that has two 6-bit inputs,

VHDL code in equations form Arithmetic Comparison Design A comparator compares the VHDL code in equations form

Arithmetic Comparison Design A comparator compares the relative sizes of two numbers. Consider a comparator that has two 6-bit inputs, A and B, which represent unsigned binary. It produces three outputs: AeqB which is set to 1 if A = B. (should be design using ONLY MUX). =

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