Question: We are studying two implementations of a machine, one with and one without special floating-point hardware. Consider a program P with the following mix of

We are studying two implementations of a machine, one with and one without special floating-point hardware. Consider a program P with the following mix of operations:We are studying two implementations of a machine, one with and one

20. We are studying two implementations of a machine, one with and one without special floating-point hardware. Consider a program P with the following mix of operations Floating-point multiply Floating-point add Floating-point divide Integer instructions I 5% 5% 70% Machine MFP (Machine with Floating-point) has floating-point hardware and can therefore implement the floating-point operations directly. It requires the following number of clock cycles for each instruction class Floating point Multiply Floating point Add Floating point Divide Integer instructions 6 cycles 4 cycles 20 cycles 2 cycles Machine MNFP (Machine with No Floating Point) has no floating-point hardware and so must emulate the floating-point operations using integer instructions. Each integer instruction on MNFP takes 2 clock cycles (so its CPI is 2). The number of integer instructions needed to implement each of the floating-point operations on MNFP is as follows Floating point multiply Floating point add Floating point divide 30 integer instructions 20 integer instructions 50 integer instructions Both machines have a clock rate of 1000 MHz (a) Find the MIPS rating for both MFP and MNFP (b) If the MFP machine needs 300 million instructions for the program P, how many integer instructions are needed on the MNFP machine for the same program P? (c) What is the execution time in seconds for program P on MFP and MNFP, assuming the instruction count from part (b)

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