We are working on a C program that is run in Unix. I am confused regarding the use of Unix command makefile. "Create a makefile named "makefile" (template posted on Blackboard) It will compile "Code2_xxxxxxxxxx.c" where xxxxxxxxxx is your student id and MyLib.c. Alter the first line comment to be your information comments start with # in make files" is the part of the question that refers to this, and the blank template is

SRC1 = Code2_1000074079.c SRC2 = MyLib.c OBJ1 = $(SRC1:.c=.o) OBJ2 = $(SRC2:.c=.o) EXE = $(SRC1:.c=.e)

HFILES = MyLib.h

CFLAGS = -g

all : $(EXE)

$(EXE): $(OBJ1) $(OBJ2) gcc $(CFLAGS) $(OBJ1) $(OBJ2) -o $(EXE)

$(OBJ1) : $(SRC1) $(HFILES) gcc -c $(CFLAGS) $(SRC1) -o $(OBJ1)

$(OBJ2) : $(SRC2) $(HFILES) gcc -c $(CFLAGS) $(SRC2) -o $

I am very confused on this and would like help completing it, this "

SRC1 = Code2_1001414779.c SRC2 = MyLib.c OBJ1 = run.o OBJ2 = $(SRC2:.c=.o) EXE = $(SRC1:.c=.e)

HFILES = MyLib.h

CFLAGS = -g

all : run

run.o: MyLib.c Mylib.h #gcc $(CFLAGS) $(OBJ1) $(OBJ2) -o $(EXE) gcc -c -g Code2_1001414779.c -o Code2_1001414779.o $(OBJ1) : $(SRC1) $(HFILES) #gcc -c $(CFLAGS) $(SRC1) -o $(OBJ1) gcc -c -g MyLib.c -o MyLib.o

$(OBJ2) : $(SRC2) $(HFILES) #gcc -c $(CFLAGS) $(SRC2) -o $(OBJ2) gcc -g Code2_1001414779.o MyLib.o -o Code2_1001414779.e"

is what I have done so far, but I am not sure if it is even correct at this point.