We have a synchronous counter with counting sequence is $Q[2$:$0]=000,001,010,011,100,$ and wrapping back to $000.$ Show the block diagram with the register, the adder$/$incrementer$,$ the load muxes, and the decoder logic. $(1$ pt$)$

When the modulo$-5$ counter reaches $Q[2$:$0]=100,$ it enables a DFF shown in the following picture. Create a timing diagram that shows clk$,$ Q$[2$:$0],$ En$,$ and clk$\_$div $(2$ pts$)$

If the frequency of clk is $1$ MHz $,$ what is the frequency of clk$\_$div? $(1$ pt $)$

If the frequency of clk is $1$ MHz and if we want the frequency of clk$\_$div to be $1$ KHz $,$

what modulo$-$n counter are we designing $($i$.$e$.$ what is the value of n$)?$ Show work. $(1$ pt$)$

how many flip$-$flops at a minimum do we need for this modulo$-$n counter? Show work $(1$ pt$)$