We want to design a circuit that numerically evaluates the integral of the function Y shown...

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We want to design a circuit that numerically evaluates the integral of the function Y shown below (i.e. the area under the curve of Y) between two values of X (input parameters); X1 and X2 using a specific value of dx (also an input parameter). Y = X³ - 2*X² + 5*X + 9 assume all inputs are 32-bit integers. The circuit is to use the simple trapezoidal rule as illustrated by the following code: integral E (X1, X2, dX) X = XLY=0; Y1-0; Y2=0 ; while (X<X2) do { wwwwwwww Y1 = X**3 - 2*X**2 + 5*X + X = X + dX; Y2 = X* *3- 2*X**2 + 5*X + Y = Y + dX* (Y+Y2) / 2 ;} www. return Y; Y X1 y1y2 b) Using the relative areas shown, evaluate all the possible design points in terms of area versus latency. Assume that the cycle time will be adjusted to the Multiplier's delay. Indicate which points are non-pareto points (if any). For each design point, generate the sequence diagram with minimum latency under the specified number of resources, then specify the resources required (number of multipliers, ALUs, and Registers) and the total latency. Draw the results on one graph. (y1 + y2)* dx/2 a) 1st you need to perform semantic-preserving transformations on the code to: [10 points] Minimize latency which is proportional to the number of operations that have to be serialized because of data dependencies, 1. Resource X2 2. Reduce resources as much as possible under the minimum latency constraint. The amount of resources is proportional to the number of similar operations performed in parallel. Multiplier Adder Register X Area 4 2 2 c) Obtain the ASM chart for the design point with minimum resources (i.e. 1 Multiplier, 1 ALU, and minimum number of registers). We want to design a circuit that numerically evaluates the integral of the function Y shown below (i.e. the area under the curve of Y) between two values of X (input parameters); X1 and X2 using a specific value of dx (also an input parameter). Y = X³ - 2*X² + 5*X + 9 assume all inputs are 32-bit integers. The circuit is to use the simple trapezoidal rule as illustrated by the following code: integral E (X1, X2, dX) X = XLY=0; Y1-0; Y2=0 ; while (X<X2) do { wwwwwwww Y1 = X**3 - 2*X**2 + 5*X + X = X + dX; Y2 = X* *3- 2*X**2 + 5*X + Y = Y + dX* (Y+Y2) / 2 ;} www. return Y; Y X1 y1y2 b) Using the relative areas shown, evaluate all the possible design points in terms of area versus latency. Assume that the cycle time will be adjusted to the Multiplier's delay. Indicate which points are non-pareto points (if any). For each design point, generate the sequence diagram with minimum latency under the specified number of resources, then specify the resources required (number of multipliers, ALUs, and Registers) and the total latency. Draw the results on one graph. (y1 + y2)* dx/2 a) 1st you need to perform semantic-preserving transformations on the code to: [10 points] Minimize latency which is proportional to the number of operations that have to be serialized because of data dependencies, 1. Resource X2 2. Reduce resources as much as possible under the minimum latency constraint. The amount of resources is proportional to the number of similar operations performed in parallel. Multiplier Adder Register X Area 4 2 2 c) Obtain the ASM chart for the design point with minimum resources (i.e. 1 Multiplier, 1 ALU, and minimum number of registers).

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a SemanticPreserving Transformations python def integralFX1 X2 dx Y 0 Y1 0 Y2 0 X X1 while X X2 Y1 X ... View the full answer