What do we mean when we say that interrupts must be processed transparently? What does this involve and why is it necessary? 2. Some processors, before servicing an interrupt, automatically save all register contents. Others automatically save only a limited amount of information. In the second case, how can we be sure that all critical data are saved and restored? What are the advantages and disadvantages of each of these approaches? 3. Explain the function of a watchdog timer. Why do embedded control processors usually need this type of mechanism? 4. How are vectored and autovectored interrupts similar and how are they different? Can they be used in the same system? Why or why not? What are their advantages and disadvantages compared with nonvectored interrupts? 5. Given the need for user programs to access operating system services, why are traps a better solution than conventional subprogram call instructions? 6. Compare and contrast program-controlled I/O, interrupt-driven I/O, and DMA-based I/O. What are the advantages and disadvantages of each? Describe scenarios that would favor each approach over the others. 7. Systems with separate I/O have a second address space for I/O devices as opposed to memory and also a separate category of instructions for doing I/O operations as opposed to memory data transfers. What are the advantages and disadvantages of this method of handling I/O? Name and describe an alternative strategy and discuss how it exhibits a different set of pros and cons. 8. Given that many systems have a single bus that can be controlled by only one bus master at a time (and thus the CPU cannot use the bus for other activities during I/O transfers), explain how a system that uses DMA for I/O can outperform one in which all I/O is done by the CPU.

The instruction set architecture for a simple computer must support access to 64 KB of byte-addressable memory space and eight 16-bit general-purpose CPU registers. a. If the computer has three-operand machine language instructions that operate on the contents of two different CPU registers to produce a result that is stored in a third register, how many bits are required in the instruction format for addressing registers? b. If all instructions are to be 16 bits long, how many op codes are available for the three-operand, register operation instructions described above (neglecting, for the moment, any other types of instructions that might be required)? c. Now assume (given the same 16-bit instruction size limitation) that, in addition to the instructions described in (a), there are a number of additional two-operand instructions to be implemented, for which one operand must be in a CPU register while the second operand may reside in a main memory location or a register. If possible, detail a scheme that allows for at least 50 register-only instructions of the type described in (a) plus at least 10 of these two-operand instructions. (Show how you would lay out the bit fields for each of the machine language instruction formats.) If this is not possible, explain in detail why not and describe what would have to be done to make it possible to implement the required number and types of machine language instructions. 3. What are the advantages and disadvantages of an instruction set architecture with variable-length instructions? 4. Name and describe the three most common general types (from the standpoint of functionality) of machine instructions found in executable programs for most computer architectures. 5. Given that we wish to specify the location of an operand in memory, how does indirect addressing differ from direct addressing? What are the advantages of indirect addressing, and in what circumstances is it clearly preferable to direct addressing? Are there any disadvantages of using indirect addressing? How is register-indirect addressing different from memory-indirect addressing, and what are the relative advantages and disadvantages of each?

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1. (2pts) Briefly describe what a lexeme and a token is. 2. (2pts) When can a parse tree be called "fully attributed"? 3. (2pts) Briefly describe the two levels of uses of operational semantics. 4. (2pts) In denotational semantics, what are the syntactic and semantic domains? 5. (2pts) What is the weakest precondition? 6. (10pts) Consider the following grammar: | ENDLINE ID "->" | "," 44*77 ID | "&" | "%" | Assume is the start symbol. Assume that all caps represents a token, quoted sequence of symbols lexemes, and angle brackets nonterminals. Also assume that the ENDLINE token is the groups of lexemes representing an end of line. The ID token represents ids in the "C" sense (start with letter or underscore, a sequence of alphanumeric and underscore characters). (a) Give a sentence in this language that is generated from at least 3 . (b) Show the left-most derivation for your sentence. (c) Show the right-most derivation for your sentence. (d) Show the parse tree for your sentence. 1. (2pts) Briefly describe what a lexeme and a token is. 2. (2pts) When can a parse tree be called "fully attributed"? 3. (2pts) Briefly describe the two levels of uses of operational semantics. 4. (2pts) In denotational semantics, what are the syntactic and semantic domains? 5. (2pts) What is the weakest precondition? 6. (10pts) Consider the following grammar: | ENDLINE ID "->" | "," 44*77 ID | "&" | "%" | Assume is the start symbol. Assume that all caps represents a token, quoted sequence of symbols lexemes, and angle brackets nonterminals. Also assume that the ENDLINE token is the groups of lexemes representing an end of line. The ID token represents ids in the "C" sense (start with letter or underscore, a sequence of alphanumeric and underscore characters). (a) Give a sentence in this language that is generated from at least 3 . (b) Show the left-most derivation for your sentence. (c) Show the right-most derivation for your sentence. (d) Show the parse tree for your sentence.