1. Which statments you can use out of twhw process:

1. variable assignment statements

2. if statement

3. conditional signal assignment statement

4. case statement

2. Choose a concurrent statement with not mutually exclusive conditions:

if (x1 < x2) then res<= a; else res<= b; end if;	out <= a when (sel = 000) else b when (sel = 001) else e when (sel =100);
z_out <= a when (sel = 000) else b when (sel = 001) else e when (sel =100) else X;	with S select F <= 0 when 001, 1 when others;

3. Rewrite the following VHDL-code using selected signal assignment statement:

F <= 01 when En=000 else (not a ) when En=001 else 10 when En=011 else 00;

4. Correct the syntax for following VHDL code, which implements rotate shift right by 1 bit². Add missing statements, correct the syntax and find logic errors.

library ieee;

____ieee.std_logic_1164.all;

entity test is _____ ( D_in : in ___________vector(7 to 0);

E: ___ std_logic;

D_out: out std_logic_vector(___ downto 0));

end ________;

architecture beh of test is

begin

process (E, _______)

_______

D_out := D_in; -- default case

if (E = '1') then

D_out (6) <= D_in (7);

D_out (5 downto 1) <= D_in (7 downto 2);

end if;

end _______;

end beh;