Which VEX operations can be scheduled simultaneously to make up the second VLIW instruction? The constructed schedule should satisfy the following conditions:

A. Assume infinite resources and no limit to the number of operations scheduled to a single instruction.

B. Operations that are scheduled in the same instruction should never have a case where an instruction operation writes to a register that a different instruction operation is reading from.

C. You are allowed to re-order instruction operations as long as dependencies are obeyed. An instruction operation can not be scheduled unless all of its dependencies are satisfied. Output results of an instruction are available only after it commits (as per its latency, for example, if an instruction takes 2 cycles, and is scheduled in cycle 5, its results are available in cycle 7).

D. Assume that no register renaming or pipeline support exists on the target processor.

E. You should construct the optimal schedule under the above constraints. Optimal schedule is the one that exhibits the fastest completion time, ie, the one that takes least number of slots for the schedule.

II. Assume each VLIW instruction consumes 2 cycles, calculate the average IPC, which is a ratio of total number of instructions operations executed to that of total number of cycles taken.