why is the btn$\_$sel $11$ staying while the mode switch and how can you get rid of that so it go to the second mode and string to $00.$

module calculator$\_$fsm $($

input clk$,$

input btn$\_$mode$1,$

input btn$\_$mode$2,$

input $[1$:$0]$ btn$\_$sel,

output reg $[2$:$0]$ opcode,

output reg mode,

output reg alu$\_$enable

$)$;

localparam MODE$\_1=1\text{'}$b$0$; $//$ Arithmetic operations

localparam MODE$\_2=1\text{'}$b$1$; $//$ Bitwise operations

reg current$\_$mode;

reg btn$\_$mode$1\_$last, btn$\_$mode$2\_$last;

reg $[1$:$0]$ btn$\_$sel$\_$internal;

$//$ Detect mode switch and reset btn$\_$sel

always @$($posedge clk$)$ begin

if $($btn$\_$mode$1$ && $!$btn$\_$mode$1\_$last$)$ begin

current$\_$mode MODE$\_1$;

btn$\_$sel$\_$internal b$00$; $//$ Reset to default operation

end else if $($btn$\_$mode$2$ && $!$btn$\_$mode$2\_$last$)$ begin

current$\_$mode MODE$\_2$;

btn$\_$sel$\_$internal b$00$; $//$ Reset to default operation

end else begin

btn$\_$sel$\_$internal btn$\_$sel; $//$ Retain btn$\_$sel

end

btn$\_$mode$1\_$last btn$\_$mode$1$;

btn$\_$mode$2\_$last btn$\_$mode$2$;

end

always @$(*)$ begin

alu$\_$enable $=0$; $//$ Default disable ALU

case $($current$\_$mode$)$

MODE$\_1$: begin

mode $=0$; $//$ Arithmetic Mode

case $($btn$\_$sel$)$

$2\text{'}$b$00$: opcode $=3\text{'}$b$000$; $//$ Addition

$2\text{'}$b$01$: opcode $=3\text{'}$b$001$; $//$ Subtraction

$2\text{'}$b$10$: opcode $=3\text{'}$b$010$; $//$ Multiplication

$2\text{'}$b$11$: opcode $=3\text{'}$b$011$; $//$ Division

default: opcode $=3\text{'}$b$000$; $//$ Default to Addition

endcase

alu$\_$enable $=1$;

end

MODE$\_2$: begin

mode $=1$; $//$ Bitwise Mode

case $($btn$\_$sel$)$

$2\text{'}$b$00$: opcode $=3\text{'}$b$100$; $//$ AND

$2\text{'}$b$01$: opcode $=3\text{'}$b$101$; $//$ OR

$2\text{'}$b$10$: opcode $=3\text{'}$b$110$; $//$ Shift Left

$2\text{'}$b$11$: opcode $=3\text{'}$b$111$; $//$ Shift Right

default: opcode $=3\text{'}$b$100$; $//$ Default to AND

endcase

alu$\_$enable $=1$;

end

default: begin

mode $=0$;

opcode $=3\text{'}$b$000$;

alu$\_$enable $=0$;

end

endcase

end

endmodule

$`$timescale $1$ns $/1$ps

module calculator$\_$fsm$\_$tb$()$;

reg clk$,$ btn$\_$mode$1,$ btn$\_$mode$2$;

reg $[1$:$0]$ btn$\_$sel;

wire $[2$:$0]$ opcode;

wire mode;

wire alu$\_$enable;

calculator$\_$fsm uut $($

$.$clk$($clk$),$

$.$btn$\_$mode$1($btn$\_$mode$1),$

$.$btn$\_$mode$2($btn$\_$mode$2),$

$.$btn$\_$sel$($btn$\_$sel$),$

$.$opcode$($opcode$),$

$.$mode$($mode$),$

$.$alu$\_$enable$($alu$\_$enable$)$

$)$;

$//$ Clock generation

initial begin

clk $=0$;

forever #$5$ clk $=$ ~clk; $//10$ ns clock period

end

$//$ Test sequence

initial begin

$//$ Initialize inputs

btn$\_$mode$1=0$;

btn$\_$mode$2=0$;

btn$\_$sel $=2\text{'}$b$00$;

$//$ Wait for some time before starting

#$10$;

$//$ Step through all operations in Arithmetic mode

btn$\_$mode$1=1$; #$10$ btn$\_$mode$1=0$; $//$ Select Arithmetic mode

#$10$ btn$\_$sel $=2\text{'}$b$00$; $//$ Addition

#$10$ btn$\_$sel $=2\text{'}$b$01$; $//$ Subtraction

#$10$ btn$\_$sel $=2\text{'}$b$10$; $//$ Multiplication

#$10$ btn$\_$sel $=2\text{'}$b$11$; $//$ Division

#$10$;

$//$ Step through all operations in Bitwise mode

btn$\_$mode$2=1$; #$10$ btn$\_$mode$2=0$; $//$ Select Bitwise mode

#$10$ btn$\_$sel $=2\text{'}$b$00$; $//$ AND

#$10$ btn$\_$sel $=2\text{'}$b$01$; $//$ OR

#$10$ btn$\_$sel $=2\text{'}$b$10$; $//$ Shift Left

#$10$ btn$\_$sel $=2\text{'}$b$11$; $//$ Shift Right

$//$ End simulation

#$50$ $finish;

end

endmodule