WILL THUMBS UP QUICK PLEASE ANSWER A AND B THANKS PLEASE REALLU FAST For the $4-$bit adder below, each FA block uses the full$-$adder circuit in the previous problem. $4-$bit

inputs $A(3$:$0),B(3$:$0),$ and the carry$-$in bit $C_0$ arrive at the same time. The bits of $A(3$:$0),B(3$:$0),$ and

$C_0$ can be $0$ or $1.$ You may find the full$-$adder stage logic diagrams below useful.

a$.$ Determine the maximum time delay from when $A(3$:$0)$ and $B(3$:$0)$ arrive until output $S_1$ is valid.

Put your final answer here.

Delay $=$

b$.$ Determine the maximum time delay from when $A(3$:$0)$ and $B(3$:$0)$ arrive until output $C_2$ is valid.

Put your final answer here.

Delay $=$