With this expression Z $=$ A'B'C'D'$+$BCE'$+$A'BE$+$A'CD$+$B'CDE

a$)$ Draw the schematic logic circuit for your derived expression using only $2-$inputs basic logic gates from Quartus II$.$

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b$)$ Simulate the schematic logic circuit for your derived expression using Quartus II$.$ Compare your waveform simulation results with the Truth Table in Question $($a$)$ and provide comments.