Question: Write a behavioral Verilog code for a 3 times 8 decoder, and then write a gate level (structural) hierarchical model of a 4 times 16

Write a behavioral Verilog code for a 3 times 8 decoder,

Write a behavioral Verilog code for a 3 times 8 decoder, and then write a gate level (structural) hierarchical model of a 4 times 16 decoder circuit constructing from two of the 3 times 8 decoders you wrote in (a), according to the following diagram

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