Write a code in VHDL that compiles in Quartus Prime and simulates in ModelSim.Please use all the original inputs and their symbols, create all files and top entity too. $1.$ Using VHDL$,$ and targeting the Altera DE$0-$CV board, create a VHDL circuit for the timer system.

$2.$ Your VHDL MUST adhere to the following guidelines:

a$.$ No integers types

b$.$ No latch warnings

c$.$ Hierarchical design and components for the delay unit, counter and display drivers.

In this lab, the concept of designing mechanism to keep track of time will be investigated. In a digital design, there are many applications that require a mechanism that is capable of tracking time. A timer and$/$or counter is useful for a variety of tasks where a delay is required.

The technical objective of this lab will be met through the design and implementation of a presettable $100$ millisecond timer in VHDL$.$

Pre$-$Laboratory: $(30\backslash \%)$

The block diagram below represents the timer system.

$-$ The mux chooses the constant that will be used by the delay unit. The $100$ ms constant is used for the hardware implementation of the timer, the $100$ns constant is used for simulation. Use lecture $13$ as a guide for determining the two constants for MAX$\_$COUNT.

$-$ The delay unit creates a $1$ clock cycle pulse at the interval defined by its delay input $($every $100$ ms or every $100$ ns $).$ Use lecture $13$ as a guide for writing this block

$-$ The counter is a $10$ bit binary $($not BCD$)$ counter that counts to $999$ and then rolls over. It only increments when its enable input is $1.$ Use lecture $13$ as a guide to using an enable input in a synchronous process and rolling over a counter at a max value. The counter can be preset to any value between $000$ and $999$ by putting the preset value on the $10-$bit time input and activating the set$\_$n input. Note that when set$\_$n is active, the internal count $($not the output count$)$ should be set to the value on the time input. Set$\_$n should be synchronous to the clock.

$-$ The binary$2$ssd component converts a $10$ bit binary number into the seven segment display constants. Lab $6$ will be helpful in writing this component. Note that count is always an unsigned number, so you do not have to worry about a negative sign in the display.