Write a complete module description for a 5 to 1 multiplexer using procedural verilog code (b)Write the complete verilog description for a 20 to 1 mulitplexer using modules from part (a) 3. Write the equivalent structural verilog code for the procedural code below that does a y = 1+x function. input [2:0] x; output [6:0] y; reg [6:0] y; wire [2:0] x; always @(x) begin end y=0; case(x) end case 3'b000: y=1; 3'b001: y=2; 3'b010: y=9; 3'b011: y=28; 3'b100: y=65; default: y=0; Ac