Write a module named labK that implements and tests a 2-bit comparator. In the module you define two wires Gr and Eq such that Gr is true when and only when a>b and Eq is true if a==b. Use the assign keyword to implement it.

Hints

You do it in two phases. In the first you implement an one bit comparator and in the second you extend it to two bits.

Phase I (1-bit)

Define two 1-bit registers a and b and two wires Gr and Eq. The truth table for the comparator is

a	b	Gr	Eq
0	0	0	1
0	1	0	0
1	0	1	0
1	1	0	1

The boolean expressions to implement this circuit are

 Gr = ab' Eq = ab + a'b' 

Have a double for loop to assign values to a and b and display the outcome with $display so that the output looks like

a=0, b=0 -> Gr=0, Eq=1 a=0, b=1 -> Gr=0, Eq=0 a=1, b=0 -> Gr=1, Eq=0 a=1, b=1 -> Gr=0, Eq=1 

Phase II (2-bit)

Modify your definitions of registers a and b as well as wires Gr and Eq so that they are two bits wide. Also define two 1-bit wires GR and EQ. The boolean expressions driving these two wires are

 GR = Gr1 + Eq1 Gr0 EQ = Eq1 Eq0

Use again the $display system task to print out the results which should look like

a=00, b=00 -> GR=0, EQ=1 a=00, b=01 -> GR=0, EQ=0 a=00, b=10 -> GR=0, EQ=0 a=00, b=11 -> GR=0, EQ=0 a=01, b=00 -> GR=1, EQ=0 a=01, b=01 -> GR=0, EQ=1 a=01, b=10 -> GR=0, EQ=0 a=01, b=11 -> GR=0, EQ=0 a=10, b=00 -> GR=1, EQ=0 a=10, b=01 -> GR=1, EQ=0 a=10, b=10 -> GR=0, EQ=1 a=10, b=11 -> GR=0, EQ=0 a=11, b=00 -> GR=1, EQ=0 a=11, b=01 -> GR=1, EQ=0 a=11, b=10 -> GR=1, EQ=0 a=11, b=11 -> GR=0, EQ=1 

Finaly, define an oracle that computes the outcome and compares it with the result of the comparator and prepends the words PASS or FAIL accordingly and this should look like

PASS: a=00, b=00 -> GR=0, EQ=1 PASS: a=00, b=01 -> GR=0, EQ=0 PASS: a=00, b=10 -> GR=0, EQ=0 PASS: a=00, b=11 -> GR=0, EQ=0 PASS: a=01, b=00 -> GR=1, EQ=0 PASS: a=01, b=01 -> GR=0, EQ=1 PASS: a=01, b=10 -> GR=0, EQ=0 PASS: a=01, b=11 -> GR=0, EQ=0 PASS: a=10, b=00 -> GR=1, EQ=0 PASS: a=10, b=01 -> GR=1, EQ=0 PASS: a=10, b=10 -> GR=0, EQ=1 PASS: a=10, b=11 -> GR=0, EQ=0 PASS: a=11, b=00 -> GR=1, EQ=0 PASS: a=11, b=01 -> GR=1, EQ=0 PASS: a=11, b=10 -> GR=1, EQ=0 PASS: a=11, b=11 -> GR=0, EQ=1 

Hints

The first two modules are relatively easy to write and debug. The third, which uses gate instantiations is a bit tricky. Make sure that you give various wires names that indicate their role in the module like

 wire abc, nanbc, anbnc, nabnc, na, nb, nc; 

so that it is easy to remember that nb is not b and nanbc is not a and not b and c.

Style

Your file should include a header that includes your name, section, today's date and a very brief description of what it does (no more than 2 lines).

Indentation is very important. Every sub-block should be indented in a consistent way. Many errors are due to the incorrect matching of begin-end pairs

The above conventions are not just style. Code that does not observe them will fail at some point.

Whenever a structure in your program is not immediately obvious, you should have a short comment explaining it. Too many empty lines make the code unreadable and long sequences of Verilog statements, especially if they are not closely related are worse. Leave an occasional empty like to break long sequences in meaningful places.