Write a RISC$-$V program that implements a unique display on the development board. Upon programming the FPGA, the right$-$most $7-$segment display on the development board blinks the value of $0$ at about a $2$Hz rate. This blinking continues with any digit value so long as the lower button on the dev board is not pressed. When the lower button is pressed and the right$-$most switch is in the up position, the digit increments once per clock cycle; if the digit is at $9,$ the digit automatically rolls over to $0$ and continues counting from that value. When the button is pressed and the right$-$most switch is in the down position, the digit decrements; if the digit is at $0,$ the digit automatically rolls under to $9$ and continues to count from that value. All counting should be once per clock cycle. This process continues ad nauseum. The count should appear on only one $7-$segment display.

$$ All numbers positions should blink with a $50\%$ duty cycle at least one time

$$ This is an open$-$ended problem; your main task is to write this program and show that it works on the Basys$3$ board so don$$t get too hung up on details

$$ Use the wrapper associated with Experiment $5$

$$ Include a flowchart and a complete written description of the algorithm your solution uses

$$ Minimize the amount of code you use in your solution