Question: Write a thermometer to gray code converter in VHDL. The architecture body of the third design must be based primarily on a loop statement inside

Write a thermometer to gray code converter in VHDL. The architecture body of the third design must be based primarily on a loop statement inside a process. It must consider don't cares. Entity has ports

therm : in std_logic_vector(6 downto 0);

out : std_logic_vector(2 downto 0)

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