write a verilog code for the following sequence detector. The finite$-$state machine $($FSM$)$ has a $1-$bit input v and $1-$bit output g$.$ For each $4-$bit input sequence, the output is $0$ for the first three bits, then $1$ on the fourth bit if the $4-$bit sequence matches one of the binary strings $1111,1010,$ or $1101.$ This is a Mealy$-$type FSM$.$ The machine returns to the reset state after each $4-$bit sequence. Note that the input patterns do not overlap.

Some sample behavior of the finite state machine is the following. The example puts a space between each $4-$bit input sequence to make them easy to see.

v $=111110000100011110101001...$

g $=000100000000000000010000...$

$2.$ Fully reduce the number of states in your FSM