Write a Verilog module consistent with the course style guide that does the following:

For now, it has an empty port list.

Creates a $10-$bit storage location for a count value.

Has an al ways biock that responds to two placeholder signals $($we will insert these names during the lab$).$ One of these signals resets the count to $0,$ and the second increments the count.

Has a second always block that implements the gray code conversion discussed in the introduction