Write a Verilog program and a Test Bench for this simple Mealy State Machine.

Serial Data Code Conversion NRZ-Code to Manchester-Code Mealy machine implementation Use Clock2, twice the frequency of the basic clock OIf the NRZ bit is 0 (1), it will be 0 (1) for two Clock2 periods NRZ data Manchester data Converter Clock2 Manchester (ideal) 110 10 1 0010 11 1 0 0 1 Clock2 s) 0 % Z (actual) PresentNext State Output Z 1 clock period glitch (false output) So S1 S2 So So 27