Write a VHDL code that meets the following requirements: design a music box, which satisfies the minimum requirements below.

$1.$ Users are able to select and switch between any one of the three

modes $($Mode A$,$ Mode B and Mode C$)$ to play music.

$2.$ Stop button$/$switch works for all three modes.

$3.$ LEDs work for all three modes.

$4.7-$Segment Display works for all three modes.

$5.$ Only one mode can be active at any time.

$6.$ Your system should handle when users don$$t follow rules. $($Error

Handling: Your system should never break down.$)$

Mode A $($Default Mode$)$:

$1.$ Music is played by switches.

$2.$ Putty on your PC should show the tones being played timely.

$($You need to tune the frequency for sending each

$($numbered$)$ note character$$ back to Putty so that the melody

is readable from Putty.$)$

Mode B:

$1.$ Music is played from Bram.

$2.$ Putty on your PC should show the tones being played timely.

Mode C:

$1.$ Music is played by users entering numbered music notation on

Putty.

$2.$ Each numbered music notation transmitted from Putty should

play $0\mathrm{.}5$ seconds.

$3.$ Each numbered music notation entered should be echoed

back to Putty. $($Lab $2)$

$4.$ The system should handle when users enter invalid

characters. components entities: entity receiver is

port $($

clk : in std$\_$logic; $--$ clock input

reset : in std$\_$logic; $--$ reset, active high

sdata : in std$\_$logic; $--$ serial data in

pdata : out std$\_$logic$\_$vector$(7$ downto $0)$; $--$ parallel data out

ready : out std$\_$logic $--$ ready strobe, active high

$)$;

end receiver; entity transmitter is

port $($ clk : in std$\_$logic; $--$ clock input

reset : in std$\_$logic; $--$ reset, active high

pdata : in std$\_$logic$\_$vector$(7$ downto $0)$; $--$ parallel data in

load : in std$\_$logic; $--$ load signal, active high

busy : out std$\_$logic; $--$ busy indicator

sdata : out std$\_$logic$)$; $--$ serial data out

end transmitter; entity SwitchPiano is

Port $($

clk : in std$\_$logic; $--$ clock input

reset : in std$\_$logic; $--$ reset, active high

switch : in std$\_$logic$\_$vector$(7$ downto $0)$; $--8$ switches

stop : in std$\_$logic;

LED : out std$\_$logic$\_$vector$(7$ downto $0)$;

freq : out std$\_$logic; $--$ Audio output

gain : out std$\_$logic; $--$ Gain control

shutdown : out std$\_$logic $--$ Shutdown control

$)$;

end SwitchPiano; entity AutoPiano is

Port $($

Clk : in STD$\_$LOGIC;

switch : in STD$\_$LOGIC$\_$VECTOR $(7$ downto $0)$;

stop : in STD$\_$LOGIC;

freq : out STD$\_$LOGIC;

LED : out STD$\_$LOGIC$\_$VECTOR $(7$ downto $0)$;

gain : out STD$\_$LOGIC;

shutdown : out STD$\_$LOGIC;

an: out STD$\_$LOGIC$\_$VECTOR$(3$ downto $0)$;

cat: out STD$\_$LOGIC$\_$VECTOR$(6$ downto $0)$;

note$\_$in : in STD$\_$LOGIC$\_$VECTOR$(3$ downto $0)--$ Input note from memory

$)$;

end AutoPiano;