Write another Parametrizable Verilog code that utilize the $1^{st}$ module $($the absolute

difference$)$ to compute the sum of squares of absolute difference of $4$ inputs as:

$Y=(|A-B|{)}^2+(|C-D|{)}^2$

Make sure you properly adjust the width $($i$.$e$.$ number of bits$)$ of $Y.$

module S$\_$absdiff #$($parameter $n=4)($input $n-1$:$0$ A$,$ B$,$ C$,$ D$,$ output $[2*$n:$0]$ Y$)$; $($submit S$\_$absdiff$.$v$)$

Write a testbench to test this circuit with following values:

$A=4,B=8,C=9,D=5,$ and $A=9,B=9,C=15,D=0.$

module S$\_$absdiff$\_$tb; $($submit S$\_$absdiff$\_$tb$.$v$)$