Write the answers on your answer sheets.$$

$($a$)$ Briefly explain the terms mobility degradation and velocity saturation.

$($b$)$ A design implemented in a $180$ nm CMOS process has a frequency $200$ MHz$,$ area $2$ sq$.$ mm$,$ and switching power $40$ mW$.$ The design is expected to be retargeted to a newer $90$ nm process. Assuming Dennard scaling model and ignoring the interconnect, what are the expected frequency, area, and switching power.

$($c$)$ A $16$ nm FinFET process has fin height and thickness of $32$ nm and $8$ nm respectively.$$ How many fins are need to obtain an effective transistor width of $144$ nm$.$

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