Write the Boolean equation for the circuit shown in Figure A8 in the Sum Of Product (SOP) form. (b) List all the variables, and all the literals in the Boolean function obtained in part (a). (c) Represent the Boolean equation from part (a) in a three variable Karnaugh map and then simplify it as one product term. (d) Assuming each gate has a delay of 0.2 ns, compare the original circuit and the simplified form by calculating the number of transistors and delays of both circuits. (e) Convert the simplified circuit from part (b) to a truth table. (f) Have we done here optimisation or trade-off? Explain your