Write the SystemVerilog code (modules) for each of the following circuits. Type the answers to this question when possible, and minimize the number of lines of code that you use.

(a) 4-input AND gate. Inputs: a, b, c, d. Output: y. Module name: and4. Hint: the SystemVerilog operator for AND is &.

(b) 4-input XOR gate. Inputs: a, b, c, d. Output: y. Module name: xor4. Hint: the SystemVerilog operator for XOR is ^.

(c) 4-input NOR gate. Inputs: a, b, c, d. Output: y. Module name: nor4. Hint: you would write the 2-input NOR operation as: assign y = ~(a | b); .

(d) Implement the function: y = a & b | c & d & ~e. Name the module: func1.

(e) Implement the bit-wise and of a[3:0] and b[3:0]. The output should be: y[3:0]. Name the module and4bit.

(f) Implement a circuit that reverses the bits of input a[3:0] and outputs the result to y[3:0]. Name the module reverse. Hint: to concatenate bits, use {}. For example, to swap the left two bits with the right two bits, you would write: assign y = {a[1:0], a[3:2]}; . To pick off bit 0 only, you would write: a[0]