Write the truth table and draw the circuit represented by

$F=(B+D)(A+B^{\text{'}}+C)+(B+D)(C+A)$

$($a$)$ Write the equivalent min term and max term expressions.

$($b$)$ Use K$-$map to find the simplest sum of product expressions. Use K$-$map of the complement to

find the simplest of product of sums expression for $F.$

$($c$)$ Write a circuit for $F$ in terms of AND, OR and NOT gates and then convert it to circuit in terms

of NAND gates.

$($a$)$ Draw the state diagram for a FSM with states $x$ mod $7,$ and the transitions are $x2x+1$ mod $7$ or

$x3x+2$mod$7$ based on some binary input I, the outputs $(Z_1,Z_2)$ are $(2$xmod$3,x+1$mod$2)$

and $(2x+1$mod$3,$xmod$2)$ respectively.

$($b$)$ Encode the states of the FSM by bits. List your encoding in a table or show the encoding on your

diagram.

$($c$)$ Write the truth table for the next state function and the outputs.

$($d$)$ Implement circuit for next state using a decoder.

$($e$)$ Implement circuit for the output $Z_1$ using $8-1$ multiplexers.

$($f$)$ Implement circuit in terms of AND, OR$,$ NOT gates for $Z_2$ using the simplest SoP formula for $Z_2$

$($g$)$ Use the above circuits to implement the FSM

Draw the timing diagram for $Q,$ that $Q(t)$ as a function of time give the diagrams for a gated SR Latch

A multi$-$cycle processor $P1$ executes load instructions in $8$ cycles, store instructions in $7$ cycles, arith$-$

metic instructions in $5$ cycles, and branch instructions in $4$ cycles. Consider an application A where

$25\%$ of all instructions are load instructions, $20\%$ of all instructions are store instructions, $40\%$ of all

instructions are arithmetic instructions, and $15\%$ of all instructions are branch instructions. A new

design of the processor doubles the clock frequency of $P1.$ However, the latencies of the memory

instructions increase by $2$ cycles, ALU instructions decrease by $1$ cycle and branch instructions in$-$

crease by $1$ cycle. We call this new processor $P2.$ The compiler produce $1E7$ instructions to run the

application. Thre frequency of $P1$ is $5GHz.$

$($a$)$ What is the global CPI for each implementation?