Write two versions of a Verilog module that takes a parameterized n$-$bit number and outputs a

single bit that indicates if the input is an even number. In the frst one, you can just look at the least

signifcant bit. In the second version, perform some other operation to determine the $$evenness$$ of

the input. The module $$signature$$ is shown below for consistency. $($If you need to make the output

a reg, go ahead and do that.