WRITE VERILOG CODE FOR FOLLOWING STATE MACHINE CHART AND following EQUATIONS FROM STATE MACHINE CHART: (2 FLIP FLOPS USED)

Q₁⁺ = Q1Q0X2(X1+X3)+Q1Q0X2

Q₀⁺ = Q1Q0X2+Q1Q0X3X2X1+Q1Q0X1+Q1Q0X2 = Q₁Q₀X₂+ Q₁Q₀X₂ (X₁+ X₃)

Z1 = Q₁Q₀X₂ + Q₁Q₀ + Q₁Q₀= Q₁Q₀X₂ + Q₀ +Q₁ Note, for first term, next input required

Z2 =

Z3 =

...Include top level module, clk, and submodule for flip flop states...

TOP MODULE EXAMPLE:

module SM (

input X3,

input X2,

input X1,

input PBC,

output Z3,

output Z2,

output Z1,

output q1,

output q0,

output [7:0] SSEG_CA,

output [7:0] SSEG_AN );