Xilinx MUX Design. This is not a Python program. Xilinx is used for this program

General Description: You are to create an 8-to-1 MUX using 7 instances of the Xilinx 2-to-1 MUX module named (M2_1) in the library of parts. You design will have eight data inputs, one bit each (d7d0). There will be one output, also being 1-bit (y). The MUX is to be created using ONLY 2-to-1 MUXs, having two data inputs (one bit each) and one output, also being 1-bit. The purpose of this lab is to use structural modeling techniques with the schematic editor. The unconnected structure of the 8-to-1 MUX is shown in the diagram below:

For the simulation, you must place the value 110010102 on inputs d7 to d0, and the go through all 8 combinations of the selected lines, s2 to s0.

You may modify the following Testbench:

// Initialize Information Inputs

//you may give different values

d0 = 0; d1 = 1; d2 = 0; d3 = 1; d4 = 0; d5 = 0; d6 = 1; d7 = 1; s0 = 0; s1 = 0; s2 = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#10 s2 = 0; s1 = 0; s0 = 0;

#10 s2 = 0; s1 = 0; s0 = 1;

#10 s2 = 0; s1 = 1; s0 = 0;

#10 s2 = 0; s1 = 1; s0 = 1;

#10 s2 = 1; s1 = 0; s0 = 0;

#10 s2 = 1; s1 = 0; s0 = 1;

#10 s2 = 1; s1 = 1; s0 = 0;

#10 s2 = 1; s1 = 1; s0 = 1;