You are asked to elaborate on possible data path abstractions for the following segment of a loop-body that is to be executed several times. These four assignments in the model can be broken down into a set of simple operations such as addition, subtraction, multiplication and comparison. . a) Construct a data flow graph (DFG) representing this code. b) Schedule the DFG to achieve a minimum number of control steps. c) Find the minimal number of registers for variable-register binding. d) Draw a data path structure implementing the scheduled DFG representation. Operations can be folded into ALUs. Show the MUXes, ALUs, and registers and their interconnections in your design.4 e) [Bonus] Elaborate on other possible implementations of this code based on various technologies considering cost, performance, size, and power requirements and any other factors. Is there a single best design for it?