You are designing a simple virtual memory system for used in your upcoming high performance embedded processor to support multiple processes running concurrently. Your processor has the following initial design: e $16-$bit architecture, with $16-$bit virtual address space. e Multiple versions of the processor exists, each processor may be populated with $128$ MiB to $1$ GiB of physical SRAM. In all cases, physical memory addresses are always $30$ bits. @ No cache. e Unified TLB: $8$ entries, fully associative, true LRU. e $1$ KiB pages.