You are given a test bench module for the finite state machine listed in part a. i. What is the expected output sequence, z? ii. What is the duration of the test run? ii. What state will the module listed in (a) end with?

`timescale 1ns/1ns

module Exam_tb ();

reg Tclk, RST, A, B;

wire Z;

EXAM_SM UUT ( .CLOCK(Tclk),

.RESET(RST),

.A(A),

.Z(Z) ); // instantiate UUT

always begin // create freerunning test clock with 10 ns period

#6 Tclk = 0; // 6 ns high

#4 Tclk = 1; // 4 ns low

end initial begin // What to do starting at time 0

$monitor("Time:%d RST=%b Tclk=%b A=%b Z=%b",

$time, RST, Tclk, A, Z); // Monitor all signals

RST = 1; // Apply reset

A = 1; // A is 1

Tclk = 1; // Start clock at 1 at time 0

#20; // Wait 20 ns

RST = 0; // unreset

A = 0; #10;

A = 1; #10;

A = 0; #10;

A = 1; #10;

A = 1; #10;

A = 0; #10;

A = 0; #10;

A = 1; #10;

$stop(1); // end test

end

endmodule