You are going to build a FIFO buffer circuit based on a register file.

$1)$ Implement a $12-$register register file. Each register needs to be $8$ bits wide. There needs to be one read

port and one write port.

The FIFO must be capable of holding $12$ data elements at a time before becoming full.

$2)$ Use this register file as part of the datapath of a FIFO buffer. Add a control path as well. The inputs are:

Din $8$ bits

Push $$ adds Din to the end of the FIFO buffer on the next rising clock edge

Pop $$ removes the first element from the FIFO buffer on the next rising clock edge

Clk

The outputs are:

Dout $$ the value of the first FIFO element

Full $$ true if the FIFO is full

Empty $$ true if the FIFO is empty

$3)$ Implement the datapath and control path

$4)$ Create a testbench and test it$.$

$5)$ Turn in the modules, testbench, and simulation evidence that it works.