You have a signed $4-$bit number A and an unsigned $4-$bit number B in $2$s

complement number system. You know that A is always non$-$positive, e$.$g$.,$ zero

or negative. Now, design the $($absolute$)$ magnitude comparator by modifying the

magnitude comparator you have studied from the class. Please modify the circuit

below to perform the $($absolute$)$ magnitude comparator. Note you do not need to

consider the case that A is a positive number

Questions $(100$ points$)$

Please solve the following questions.

$(1)$ Prove the equality of the left and right terms of the following equations. $(10$

points$)$

$(($A$*$B$)+($A$*$C$)+($B$*$C$))*(()/($bar$)($A$*$B$*$C$))=($A$*$B$(*)/($b$)$ar $($C$))+($A$*$C$(*)/($b$)$ar $($B$))+($B$*$C$(*)/($b$)$ar $($A$))$

$(2)$ Prove the equality of the left and right terms of the following equations. Note A$^(\text{'})$

is not$($A$).(10$ points$)$

$(3)$ Draw the gate level schematic of the right term in $(2).$ Assume you already have

A$^(\text{'}),$B$^(\text{'}),$C$^(\text{'})($no need to draw an inverter$).(10$ points$)$

$(4)$ Draw the right term of $(2)$ to have the equivalent delay of the inverter whose

NMOS and PMOS are sized $1$ and $2,$ respectively. Assume that the signal

arrival time is in the order of B$->$C$->$ A$.(10$ points$)$

$($Total: $40$ points$)$