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Q$1(6$ points$)$ Implement $f(a,b,c)={\displaystyle \underset{?}{\overset{?}{}}}(0,1,7)$ and $g(a,b,c)={\displaystyle \underset{?}{\overset{?}{}}}(0,1,3,4,5,7)$ using one decoder and minimal number of gates.

Q$2(6$ points$)$ Consider an $8-$to$-1$ multiplexer with eight data inputs $d_0$ to $d_7,$ three select inputs $S_2,S_1,$ and $S_0,$ and one output $Y.$

a$)$ Write the logic expression for the output $Y.$

b$)$ Implement an $8-$to$-1$ multiplexer using only $2-$to$-1$ multiplexers.

Q$3(6$ points$)$ Implement the function $f(a,b,c,d)={\displaystyle \underset{?}{\overset{?}{}}}(0,1,5,7,8,10,13,14,15)$ using an $8-$to$-1$ multiplexer and minimal number of gates.

Q$4(5$ points$)$ Using $8-$bit adders and minimal number of additional gates, draw a circuit that adds three $8-$bit signed integers $A_{{?}_{?}}[7$:$0],0_{{?}_{?}}7$:$0,$ and $C_{{?}_{?}}7$:$0.$ The circuit should output an $8-$bit result $R_{{?}_{?}}[7$:$0]=A_{{?}_{?}}[7$:$0]+B_{{?}_{?}}77$:$0$ and an overflow flag V if there is overflow in the $8-$bit result.

Q$5(7$ points$)$ Answer the following questions:

a$)$ If a clock has a cycle $=2ns,$ what is the clock frequency? Show your work.

b$)$ If a clock has a frequency $=5GHz,$ what is the clock cycle? Show your work.

c$)$ Show the timing of a D$-$Latch with clock input $($Glk$)$ by showing the output $Q$ in the timing diagram. Assume that $Q$ is initially $0.$

d$)$ Show the timing of a positive edge$-$triggered D Flip$-$Flop by showing the output $Q$ in the timing diagram. Assume that $Q$ is initially $0.$