You$$re analyzing the simple data memory we discussed in the lectures $(2$ bit word level addressing and $8$ bit words$).$ Consider the following timing diagram: CLK A WE WD $0$x$00$x$30$x$20$x$00$ A B C D E F G $0$xEF $0$x$00$x$30$x$12$ For each point indicated on the timing diagram, draw an $$array of words$$ representation for the memory contents and determine the value of the RD bus. When the memory first powers on$,$ the value of the registers are undefined and you can represent them with a $?$