You should only submit a single Verilog file named with your R Number (ex: R01147848.v) and the module inside the file should start with the module declaration: module less_than(A, B, F);If your verilog module does not meet these two requirements, the testbench/grading system will not recognize your submission and you will receive a grade of 0.

Answer rating: 100% (QA)

Solution Verilog code for the above specification And the file name is R01147848v we ... View the full answer