You should write your answers as clearly and concisely as possible. For each instruction,

use figure $4\mathrm{.}35$ and add the control signals as shown in figure $4\mathrm{.}50.$ To keep the resulting

figure simple, just add the control signals that are relevant to the instruction in each

problem. One copy of figure $4\mathrm{.}35$ for each instruction should be sufficient. $(25$ points each$).$

Write your name and homework number on the top of the first page.

Implement the li I$-$type instruction on the multicycle datapath. Include your diagram,

a description, and the control signal values.

Implement the lui I$-$type instruction on the datapath. Include your diagram, a

description, and the control signal values.

Implement the jal J$-$type instruction on the multicycle datapath. Include your

diagram, a description, and the control signal values.

Implement the jr R$-$type instruction on the multicycle datapath. Include your

diagram, a description, and the control signal values FIGURE $4\mathrm{.}35$ The pipelined version of the datapath in Figure $4\mathrm{.}33.$ The pipeline registers, in color, separate each pipeline stage.

They are labeled by the stages that they separate; for example, the first is labeled IF$/$ID because it separates the instruction fetch and instruction

decode stages. The registers must be wide enough to store all the data corresponding to the lines that go through them. For example, the

IF$/$ID register must be $64$ bits wide, because it must hold both the $32-$bit instruction fetched from memory and the incremented $32-$bit PC

address. We will expand these registers over the course of this chapter, but for now the other three pipeline registers contain $128,97,$ and $64$

bits, respectively. FIGURE $4\mathrm{.}50$ The control lines for the final three stages. Note that four of the nine control lines

are used in the EX phase, with the remaining five control lines passed on to the EX$/$MEM pipeline register

extended to hold the control lines; three are used during the MEM stage, and the last two are passed to MEM$/$

WB for use in the WB stage.